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多操作数加法器是数字集成电路设计的基本算术单元之一，其逻辑优化是逻辑综合流程中至关重要的一部分。为了在逻辑综合过程中尽可能地提升多操作数加法器的性能，降低延迟，本文设计了一种基于自适应进位保留加法器(carry-save adder, CSA)的多操作数加法器架构。该架构采用Wallace树结构实现多操作数加法器的设计，降低加法操作导致的延迟，并在此基础上，通过改进Wallace树结构中的CSA压缩部分，进一步降低延迟。本文以SMIC 28nm工艺库为目标库，运用上述算法对多个多操作数相加的RTL(register-transfer level)设计执行逻辑综合，得到多操作数加法器。实验结果表明，在16～128位宽输入下，本加法器可显著优化性能，延迟时间平均降低31.2%,面积平均减少36.5%,功耗平均降低70.98%。
Abstract：Multi-operand adder is one of the basic arithmetic units of digital circuit design and its logic optimization is a crucial part of the logic synthesis process.In order to improve the performance and reduce the delay of the multi-operand adder as much as possible during the logic synthesis process, this paper designs a multi-operand adder architecture based on the adaptive CSA algorithm.The architecture uses Wallace tree structure for logic optimization of the multi-operand adder.And based on this, the delay is further reduced by improving the CSA compression part of the Wallace tree structure.In this paper, we adopt SMIC 28nm process library as the target library, and apply the above algorithm to perform logic synthesis on multiple multi-operand adder designs, and verify the effectiveness of the adder architecture by analyzing the performance of the synthesized circuit netlist.Experimental results show that the adaptive CSA-based multi-operand adder architecture can significantly optimize the performance with 16-128-bit wide inputs: latency is reduced by an average of 31.2%,area is reduced by an average of 36.5%,and power consumption is reduced by an average of 70.98%.This proves its effectiveness in reducing area and power consumption along with latency.
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基本信息:
DOI：10.20062/j.cnki.CN37-1453/N.2025.03.003
中图分类号:TP332.21
引用信息:
[1]王立华,崔可欣,付文杰,等.基于自适应CSA的多操作数加法器设计[J].鲁东大学学报(自然科学版),2025,41(03):222-232.DOI:10.20062/j.cnki.CN37-1453/N.2025.03.003.
基金信息:
山东省本科教学改革研究重点项目(Z2024099)